This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-069897, filed Mar. 16, 1999; and No. 11-076355, Mar. 19, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a method of manufacturing a MOS-type transistor or a MIS-type transistor and to a MOS-type transistor or a MIS-type transistor. More specifically, it relates to the method of forming a diffusion layer in the salicide process and to a MOS-type transistor or a MIS-type transistor which will be obtained by this method.
As a result of an increasing demand in recent years for speeding-up as well as for the realization of high performance, the formation of low-resistance refractory metal silicide film, such as TiSi2 and CoSi2, on the gate electrode and on the source-drain diffusion layer by self-alignment with the gate electrode is now being practiced. This is called the salicide structure. On the other hand there is a strong demand for miniaturization which makes it indispensable to form a diffusion area thinly on the semiconductor substrate.
Conventionally the salicide structure has been manufactured as follows. First form a polycrystal silicon layer on a silicon substrate 1 through a gate insulating film 2, and form a gate electrode 3 by patterning it (FIG. 1A). Then form a shallow impurity diffusion layer 4 by the ion-implantation of impurity by using the gate electrode 3 as a mask (FIG. 1B).
Next, form a silicon nitride film on the entire surface of a substrate, and form a side-wall insulating film 5 on the side walls of a gate electrode 3 by implementing anisotropic etching, such as reactive ion etching (RIE). Then form a deep impurity diffusion layer 6 by the ion-implantation of impurity by using the side-wall insulating film 5 as a mask, and at the same time introduce impurity into the gate electrode 3 (FIG. 1D)
After this, heat the entire structure to activate the impurity in the gate electrodes 3 and also the impurity in the impurity diffusion layers 4 and 6 at the same time. This process forms a shallow diffusion layer 7, adjacent to the gate electrode, having the so-called extension structure with a high-impurity concentration (FIG. 1E).
As the condition for activating the impurity, however, it is necessary to activate the impurity in the polycrystal silicon, which is the gate electrode, as well as the impurity in the deep impurity diffusion layer 6, all at the same time. Therefore, high temperature is required for this process, thus diffusing the shallow impurity diffusion layer 4 to a comparatively deep depth and making it difficult to maintain the shallow impurity diffusion layer at the shallow depth.
Next, form a silicide film 8 on the upper side of the gate electrode 3 and on the exposed surface of the impurity diffusion layer 7 (FIG. 1F).
As described above, the conventional technology has formed the shallow impurity diffusion layer 4 before the deep impurity diffusion layer 6 is formed, thus diffusing the impurity of the shallow impurity diffusion layer 4 to a deep depth and making it difficult to form the aimed shallow impurity diffusion layer.
In order to solve this problem, it is proposed to use the method of forming a deep impurity diffusion layer first after forming a gate side-wall insulating layer and then forming a shallow impurity diffusion layer after removing the side-wall insulating film (Ref. Kenichi Goto et al. xe2x80x9cA High Performance 50 nm PMOSFET using Decaborane (B10H14) Ion Implantation and 2-step Activation Annealing Processxe2x80x9d IEDM-97, pp. 471-474). However, this technology does not provide the gate side-wall insulating film, and therefore forms a silicide film on the side wall of the gate electrode when trying to provide a low resistance silicide film on the upper side of the gate and on the upper side of the impurity diffusion layer, resulting in a short circuit formed between the gate electrode and the impurity diffusion layer. Accordingly this structure cannot be applied to the silicide process.
Further, in this method, the side-wall insulating layer is removed by isotropic etching without covering the gate insulating film, so that an exposed portion of the gate insulating film is slightly etched. This makes the life of the gate insulating film shorter, or, at worst, a failure occurs in the gate insulating film.
The objects of this invention are to form a shallow impurity diffusion layer adjacent to a gate electrode, to provide the method of manufacturing a MOS transistor or a MIS transistor of the silicide type improved in the short channel effect, and to provide the composition of a semiconductor device which is made possible by this method.
In order to achieve the foregoing objects, a manufacturing method of a semiconductor device, which is a first aspect of the present invention, comprising the steps of:
forming a gate electrode on a semiconductor substrate through a gate insulating film;
forming a protective insulating film on a side-wall of the gate electrode;
forming a first side-wall insulating film on the protective insulating film formed on the side-wall of the gate electrode;
forming a first impurity diffusion layer on a surface of the semiconductor substrate by using the gate electrode and the first side-wall insulating film as a mask;
removing the first side-wall insulating film after the step of forming the first impurity diffusion layer;
forming a second impurity diffusion layer on the surface of the semiconductor substrate by using the gate electrode and the protective insulating film as a mask after the step of removing the first side-wall insulating film;
forming a second side-wall insulating film on the protective insulating film formed on the side-wall of the gate electrode after the step of forming the second impurity diffusion layer; and
forming a conductive film on an upper surface of the gate electrode and on a surface of the second impurity diffusion layer by using the second side-wall insulating film as a mask.
It is desirable that the step of forming the conductive film includes the step of forming a conductive film having a resistance lower than that of the second impurity diffusion layer.
It is desirable that a thickness of the first side-wall insulating film differs from that of the second side-wall insulating film.
It is desirable that a thickness of the first side-wall insulating film is smaller than that of the second side-wall insulating film.
Material of the first side-wall insulating film can be differentiated from that of the second side-wall insulating film.
It is desirable that the material of the first side-wall insulating film is SiO2 and that the second side-wall insulating film is composed of SiN.
It is desirable that the step of forming the first impurity diffusion layer and the step of forming the second impurity diffusion layer include the step of introducing and activating an impurity and a temperature of a heat treatment for activating the impurity of the first impurity diffusion layer is higher than that of the second impurity diffusion layer.
It is desirable that a diffusion distance of an impurity of the first impurity diffusion layer is longer than that of the second impurity diffusion layer.
It is desirable that the step of forming the first or second side-wall insulating film includes the step of forming a silicon oxide film and a silicon nitride film laminated thereon, and that the step of forming a conductive film on an upper surface of the gate electrode and on a surface of the first or second impurity diffusion layer includes the step of performing selective growth of silicon under a supply limited condition, and the step of performing selective growth of silicon under a reaction limited condition, after the step of performing selective growth of silicon under a supply limited condition.
It is also desirable to provide the step of etching back the silicon oxide film underneath the silicon nitride film, before the step of forming a conductive film on an upper surface of the gate electrode and on a surface of the first or second impurity diffusion layer.
It is desirable that the step of performing selective growth of silicon under a supply limited condition includes the step of performing the selective growth up to an extent where silicon-growing film becomes thicker than a film thickness of the silicon oxide film underneath the nitride film.
It is desirable to further comprise the step of removing by etching silicon particles formed on the semiconductor substrate including the side-wall insulating film, after the step of performing selective growth of silicon under a supply limited condition.
It is desirable that the gate electrode is formed of polycrystal silicon and the step of forming a first impurity diffusion layer includes the step of performing simultaneously introduction of impurity into the gate electrode and activation of the impurity.
It is desirable that the semiconductor substrate is composed of silicon and the conductive film is mainly formed of a refractory metal and silicon.
The semiconductor device, which is a second aspect of the present invention, comprising:
a semiconductor substrate;
a gate electrode formed through a gate insulating film on the semiconductor substrate;
a side-wall insulating film formed on a side of the gate electrode;
a first impurity diffusion layer formed with a first depth on a surface of the semiconductor substrate underneath the side-wall insulating film on the side of the gate electrode;
a second impurity diffusion layer formed with a second depth on the surface of the semiconductor substrate adjacent to and connected to the first impurity diffusion layer, the second depth being deeper than the first depth; and
a first conductive layer formed on a surface of the second impurity diffusion layer with an end closest to the gate electrode in contact with the outermost portion of a surface of the side-wall insulating film and formed to have a resistance lower than that of the second diffusion impurity layer; and
wherein the shortest distance between the end of the conductive layer and an end of the second impurity diffusion layer on the side of the gate electrode is greater than a distance between a bottom of the conductive layer and a bottom of the second impurity diffusion layer.
The gate electrode is desirably composed of polycrystal silicon, and has a second conductive film formed on an upper surface thereof, the second conductive film having a resistance lower than that of the gate electrode.
It is desirable that the side-wall insulating film is composed of SiN.
It is desirable that the first conductive film include a refractory metal and Si and that the refractory metal is Ti.
In the present invention, the side-wall insulating film of the gate electrode is formed twice. For this reason, it becomes possible to change the material of the side wall and the width (thickness) of a side-wall insulating film at the first time and at the second time. This makes it possible to use at the first time a side-wall insulating film suitable for enhancing the performance of a transistor and to use at the second time a side-wall insulating film of the width and material suitable for making the salicide structure for forming a silicide film on to the gate electrode and the source/drain region.
Also by forming the side-wall of a gate electrode twice, it becomes possible to embody the salicide structure for forming a silicide film on to the gate electrode and the source-drain region after forming first the portion of the impurity diffusion layer not adjacent to the gate electrode in the source-drain region and later the impurity diffusion layer adjacent to the gate electrode.
Furthermore, this makes it possible to carry out first the heat treatment required for activating the impurity diffusion layer not adjacent to the gate electrode of a transistor as well as impurity in the gate electrode, and thus to form a shallow impurity diffusion layer adjacent to the gate electrode. This brings about improvement of the short channel effect which prevents the miniaturization of a transistor, and is effective for the embodiment of further miniaturized transistor.
Also, when forming silicon as a conductive film on a secondary impurity diffusion layer, facets are not formed near the gate electrode because the initial growth is done under the supply limited condition which is changed to the reaction limited condition after it has reached the side-wall nitride film in the direction of thickness.
Further, because the initial silicon growth is done under the supply limited condition, a flat film not dependent on the crystallinity of underlying silicon is obtained. There is also an advantage that cavity is not formed underneath the nitride silicon side-wall.
The above-mentioned manufacturing method also makes it possible for the initial growth to proceed under the supply limited condition up to the extent where it does not reach the side-wall nitride film by placing a proper amount of side-etching in the oxide film underneath the side-wall nitride film prior to the selective epitaxial growth. This makes it possible to reduce the amount of side-etching to be placed underneath the nitride silicon side wall and thus to widen the margin for dilute hydrofluoric acid treatment which is the pretreatment of the epitaxial growth. Also the adoption of the elevated source-drain structure process makes it possible to easily form a silicon film which is not dependent on the underlying silicon without forming facets near the gate electrode, by combining the supply limited condition and the reaction limited condition in the selective growth process of silicon which has been carried out conventionally only either under the supply limited condition or under the reaction limited condition.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.